CV

PhD in ML Systems

• Working towards improving performance of ML inference on edge devices.
• Advised by Prof. Boris Grot and Prof. Luo Mai.

Bachelor of Technology (B. Tech) and Master of Science, Electronics and Communication Engineering (Dual Degree)

• Dean's List awardee (top 5%)
• Undergraduate Research Awardee
• Intel Andy Grove Scholarship Recipient
• CGPA := 9.01/10

Visiting Research Student

• Systematically analysed the impact of interleaving effects and co-located functions on the performance of different categories of serverless functions in a representative real-world serverless setting.
• Designed and implemented an end-to-end pipeline to explore the architectural implications of large serverless workloads at scale.
• Advised by Prof. Boris Grot, in collaboration with Dr. David Schall.

Student Researcher

• Working on research projects involving embedded systems, sensor networks, noise analysis, flexible electronics under the guidance of Prof. Aftab Hussain.
• Primarily worked on building low latency data collection systems which were used for collecting data towards driving data prediction tasks.

Student Researcher

• Worked on deploying ML models on resource constrained embedded platforms for image recognition tasks under the supervision of Prof. Suresh Purini.
• Helped develop an end-to-end pipeline for real-time image recognition using YOLOv5. Used the ONNX runtime and offloading computations to specialised accelerator cores, by which we achieved sustained performance of 90+ fps with object detection.

Research Collaborator

• Worked on analysing GPU architectures for Ray-Tracing applications using Vulkan-sim and Lumibench under the guidance of Prof. Antonio Gonzalez.
• Identified bottlenecks in the ray tracing pipeline that can potentially be solved by specific architectural modifications for SIMD and RT units as well as cache hierarchies.

TPM Intern

• Worked with the Global Capacity Management team to plan, ideate and implement a new feature for the internal tool used for staffing.
• The feature was aimed at improving the efficiency and ease of use for the requestors by providing real time feedback regarding the request specifications and suggesting similar matches based on availability using a random forest regressor.

System Software Development Intern

• Ported AM62x SoC to Zephyr RTOS from the proprietary SDK, wrote driver for proprietary RAT (Address Translation) module.
• Modified drivers for UART and Pincontrol for supporting M4F core on the AM62x. All contributions have been merged and can be found in the upstream repository -- [Zephyr RTOS](https://github.com/zephyrproject-rtos/zephyr).

Open Source Developer

• Project under the Free and Open Source Silicon Foundation (FOSSi) - [Sootty, the CLI waveform viewer](https://github.com/Ben1152000/sootty).
• Improved the temporal logic language that Sootty uses by implementing bitwise operators for multi-wire busses, adding a save flag to allow for a reusable query interface.
• Added support for ready-valid handshake detection according to the AXI protocol.

Head Teaching Assistant, Digital Systems and Microcontrollers course

• Scheduled tutorial sessions, conducted in-person lab sessions for students who take the Digital Systems and Microcontrollers course.
• Conducted hardware lab sessions and tutorials for over 300 students, headed a team of teaching assistants.
• Maintained the course website, including the lab manual and other course materials.

System Benchmark Suite

• Wrote a benchmark suite in C using vector intrinsics and some inline assembly to measure various aspects of performance of a computer system and its memory architecture, and to measure performance of various algorithms using cachegrind and perf.

Verilog Implementation of a 64-bit Y86 processor with Pipelining

• Constructed and tested two 64-bit processors with the Y86 instruction set architecture, one with sequential design and one with a full 5 stage pipeline. Tested functioning of all instructions for both. Used Verilog HDL. Project on Github -- [Y86 Processor](https://github.com/KarthikL1729/Y86-64-processor-in-Verilog)

• Dean's List awardee (top 10%) at IIIT Hyderabad

• Undergraduate Research Awardee at IIIT Hyderabad
• Dean's List awardee (top 5%) at IIIT Hyderabad
• Intel Andy Grove Scholarship Recipient